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adders and arithm...
LFSR and selftest
GAL output cell
GAL demo 1
GAL demo 2
GAL demo 3
GAL demo 4
ACT1 AND3 gate
ACT1 XOR2 gate
I/O and displays
CMOS circuits (sw...
Mips R3000 cosimu...
Intel MCS4 (i4004)
image processing ...
[Sch04] RALU, Min...
The applets in this chapter demonstrate three different topics
of programmable logic devices.
Given the ever-higher integration of semiconductor devices,
the high development costs of full-custom designs,
and factors like intellectual property protection,
programmable logic devices are often the best solution
to implement custom logic functions.
The following applets demonstrate the basic architecture
of the still popular PLA and GAL devices,
and the logic cell underlying multiplexer-based FPGAs.
Unfortunately, the planned applets on lookup-table or SRAM-based
FPGAs are not ready yet.
The first applet demonstrates the structure and organization of the so-called programmable logic array. A PLA allows creating a user-defined function based on a two-level AND-OR expansion, with the connections between input and output terms via user-programmable connections. In the applet, a fixed example connection is used.
The next five applets demonstrate the so-called generic array logic or GAL architecture. A GAL device consists of several basic cells, each of which include a programmable PLA matrix and a programmable output-cell with a flipflop. As the output of the flipflop is fed back into the PLA matrix, a GAL can be used to implement combinatorical circuits (flipflops disabled), registers, and general sequential circuits. In the applets, click on the special 'interactive transistors' to enable or disable the corresponding connection. This allows you to change the logic functions of the GALs and to create your own circuits.
The final group of four applets demonstrates the multiplexer-based logic cell used in the ACT1 family of programmable devices.
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