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Circuit Description

This circuit demonstrates how to implement a state-machine using the GAL or generic array logic structure. For a description of the circuit structure see the previous two applets.

In this demonstration, the output enable of the output cell blocks is set to low, enabling the tristate driver. Also, the SYN control bit of each output cell is selected, so that the output of the AND-OR matrix is routed into the D-flipflop in the output cell. The (inverted) output of the flipflop is routed back into the fuse matrix.

The programming in the upper GAL block implements the logical function (!C), so that the flipflop in the upper output cell toggles on each rising edge of the clock input. Similarly, the programming of the lower block implments the function (C AND D) or (!C AND !D). The total result of this programming is a two-bit binary counter.

The programming of the lower GAL block implments the XOR function of inputs A and B.

     + = fuse ok
     . = fuse blown


     A /A  B /B  C /C  D /D     function 

     .  .  .  .  .  +  .  .     /C
     +  +  .  .  .  .  .  .     0
     +  +  .  .  .  .  .  .     0
     +  +  .  .  .  .  .  .     0

     .  .  .  .  +  .  +  .     C AND D
     +  +  .  .  .  +  .  +     /C AND /D
     +  +  .  .  .  .  .  .     0
     +  +  .  .  .  .  .  .     0
                                total:   A XOR B