Applets
contents
visual index
introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation
Mips R3000 cosimu...
TinyMips int... TinyMips Sieve TinyMips stack TinyMips mul... TinyMips loa... TinyMips mul... TinyMips wit... TinyMips UAR... TinyMips UAR... TinyMips int... TinyMips int... Mips fast Sieve TinyMips wit... Mips - game ... Mips prime n... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTSThe applets in this chapter demonstrate hardware-software cosimulation of systems built around MIPS 32-bit microprocessors. The first applets use a simplified non-pipelined processor called the TinyMips, while the later applets are based on a detailed simulation model of the IDT R3051 microcontroller with instruction-pipeline and caches.
Click here for an overview of the MIPS architecture and a short description of the TinyMips simulation model. For details about the MIPS architecture visit the MIPS homepage or read one of the classic textbooks like Computer Organization and Design by David Patterson and John L. Hennessy (Morgan Kaufman ISBN: 1558604286), MIPS RISC Architecture by Kane and Heindrich (Prentice-Hall), or See MIPS run by Dominic Sweetman (Morgan Kaufman, ISBN: 1558604103).
The R3041/R3051 microcontrollers from IDT include the 32-bit MIPS processor core with five-stage instruction pipeline, separate on-chip instruction and data-caches, system-management functions. To save I/O-pins, the memory interface uses a multiplexed address- and data-bus.
The example programs for the following applets were written in the C language and compiled with the GNU gcc crosscompiler on a standard PC (i386) host. The MIPS overview page also includes a short description of the gnu toolchain and a link to a pre-built binary of the crosscompiler for linux-x86.
Note: The applets presented in this chapter should be considered a work-in-progress. You will notice that the documentation is still incomplete in places, interrupts and exception handling are not (fully) implemented, and even the simulation models are not finished.
Known Bugs: When you open the memory editor during a running simulation, a repaint is requested after each instruction fetch or load/store operation. This really shouldn't be a problem, but some JDKs (1.5.0_x) seem to dislike this, and simulator performance might break down quite a bit. Just close the memory editor(s) to run the simulation at full speed.
Help wanted! Don't hesitate to contact us should you want to work on this! Also, please mail us your suggestions, or provide updated and improved versions of the hardware structures, software, and descriptions of the applets. You can also download and study the source code of the MIPS simulation models. One very important (and interesting) enhancement would be an implementation of the C-library (e.g. based on newlib) together with a minimal "operating system". Having the C-library would make writing or porting applications to the simulator much easier.
