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|TinyMips - introduction
This applet is the first in a series of related applets
which demonstrate a complete 32-bit microprocessor system.
Please check the
for an introduction and the motiviation and concept behind these applets.
The hardware shown here consists of only two main components, namely the TinyMips microprocessor and a single MipsRAM memory component. The 32-bit wide data-bus connects the processor and the memory. The memory is controlled by the address-bus and the read-, write-, and byte-enable signals generated and driven by the processor. In this and most of the following schematics, the two main buses (address and data) and the byte-enable control signals are drawn to extend down from the processor (vertically), and memories and peripherals are connected to the left and right of those buses. The three main control signals (read-enable, write-enable, and address-latch-enable) extend from the left side of the processor.
UsagePlease wait until your browser has completed loading the applet. You should now open the GUI windows of the TinyMips processor and the MipsRAM component (use the popup-menu and select edit, or type the 'e' bindkey), so that you can watch the register contents of the processor and the read and write accesses in the main memory. Try to arrange the windows until you can watch them all. Now click the "Run" button in the simulator control panel to start the simulation.
In this applet, the clock frequency of the processor clock is set to just 1 Hz. Unlike a real pipelined processor which needs to check for and handle control- and data-hazards, the TinyMips processor always fetches and executes one instruction per input clock cycle. Due to the slow clock rate, you can easily watch the processor fetching a new instruction and updating its data-registers or reading and writing data to the main memory. If you want, you can also add probes to the clock input, the data and address bus, and the control signals, and later analyze the timing of the system-bus in the waveform viewer. The TinyMips debug-flags register is initialized with a value of 4, which activates the memory-trace messages. That is, text-messages with virtual and physical adress as well as the data values are printed to the Java console for every instruction-fetch and every load and store instruction. Unfortunately, the details of how to open the Java console depend on the web browser; for example, in Mozilla/Firefox select menu>tools>web-development>Java console. To disable those messages, simply enter a new value of 0 into the debug-flags register (address 39 in the TinyMips register view).
The program used in this applet is very simple, and consists of a single endless loop that increments some counter variables. See the link below for the source-code and the build-script used to compile, assemble, and link the program. The memory-management of the TinyMips is disabled in this applet, so that the virtual addresses used in the program are also the physical addresses actually used on the address bus. The processor is configured to fetch the first instruction from memory location 0x0000.0010, and the build-script uses the -T flag to tell the linker to relocate the first program instruction to exactly this address. Once you start the simulation, the processor reads the first instruction from memory address 0x0000.0010, and the program execution begins.
The following trace shows the first memory accesses made by the program, where if means instruction-fetch, rd means read (load word, halfword, byte), wr means write (store word, halfword, byte), va is a virtual address, and pa is the physical address after translation:
-M- if va=00000010 pa=00000010 raw=3c1d0000 -M- if va=00000014 pa=00000014 raw=0c00000f -M- if va=00000018 pa=00000018 raw=27bd0200 -M- if va=0000003c pa=0000003c raw=27bdffe8 -M- if va=00000040 pa=00000040 raw=afbf0010 -M- wr.le va=000001f8 pa=000001f8 raw=0000001c data=0000001c mode=SW -M- if va=00000044 pa=00000044 raw=0c000009 -M- if va=00000048 pa=00000048 raw=00000000 -M- if va=00000024 pa=00000024 raw=03e00008 -M- if va=00000028 pa=00000028 raw=00000000 -M- if va=0000004c pa=0000004c raw=3c02cafe -M- if va=00000050 pa=00000050 raw=3442babe -M- if va=00000054 pa=00000054 raw=24050400 -M- if va=00000058 pa=00000058 raw=00002021 -M- if va=0000005c pa=0000005c raw=3c06abba -M- if va=00000060 pa=00000060 raw=aca20000 -M- wr.le va=00000400 pa=00000400 raw=cafebabe data=cafebabe mode=SW -M- if va=00000064 pa=00000064 raw=00041027 -M- if va=00000068 pa=00000068 raw=00861821 -M- if va=0000006c pa=0000006c raw=aca40004 -M- wr.le va=00000404 pa=00000404 raw=00000000 data=00000000 mode=SW -M- if va=00000070 pa=00000070 raw=24840001 -M- if va=00000074 pa=00000074 raw=aca20008 -M- wr.le va=00000408 pa=00000408 raw=ffffffff data=ffffffff mode=SW -M- if va=00000078 pa=00000078 raw=08000019 -M- if va=0000007c pa=0000007c raw=aca3000c -M- wr.le va=0000040c pa=0000040c raw=abba0000 data=abba0000 mode=SW -M- if va=00000064 pa=00000064 raw=00041027 ...
The MipsRAM component used as the main system memory is configured to a size of 16K words (or 64 KBytes). The memory component holds the program code (text segment), but is also used for all other memory accesses (heap and stack). The default memory map is as follows:
MIPS address range | usage | -----------------------+-------------------- 0001.0000 - ffff.ffff | unused (aliased) 0000.0400 - 0000.ffff | unused | 0000.0200 - 0000.03ff | stack 0000.0100 - 0000.01ff | heap 0000.0010 - 0000.00ff | text segment (code) 0000.0000 - 0000.000f | unused
Note: the user-interface of the MipsRAM component always displays the byte addresses as used by the MIPS processor when running your programs. Internally, however, the memory uses word-addresses that correspond to the actual 32-bit locations that hold the data-words. This can be seen when you save the memory contents via the memory editor, because the resulting file is based on word-addresses. Our Elf2Rom converter tool takes care of this when creating the memory initialization files (.rom) from ELF-format program files.
Also note that no address-decoder is used; instead, the memory component is enabled for all memory accesses. Therefore, all memory accesses with addresses larger than 0001.0000 are aliased back into the lower 64 KBytes of memory.
The binary program running on the processor was compiled and linked with the GNU gcc (version 126.96.36.199) and binutils cross-compiler toolchain on a Linux x86 host. The resulting ELF format binary file was then converted via the Hades Elf2rom tool to generate the memory-dump required to initialize the MipsRAM simulation component. See:
|Print version | Run this demo in the Hades editor (via Java WebStart)|
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