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ACTEL ACT1 mux-based SR-flipflop

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Circuit Description

The ACT1 basic logic cell configured to implement a basic SR-flipflop (latch) with low-active inputs.

The output of the cell is connected via the feedback path to one input of the upper multiplexer, controlled via the /S (set) input. As the second input multiplexer is not used at all, all its inputs are connected to low level. The /R (reset) input is connected to the control input of the second-level multiplexer, whose output is used as the flipflop Q signal.

Click the input switches or type the 's' and 'r' bindkeys to control the applet.

Note that the flipflop is initialized to 'X' (undefined) in the simulation, due to the feedback through the multiplexers. In the real circuit, the flipflop will be initialized to a random state, instead.

Print version | Run this demo in the Hades editor (via Java WebStart)
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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/42-programmable/40-mux-fpga/ACT1-srff.html