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Circuit Description

This circuit demonstrates two more examples of logical functions using the GAL or generic array logic structure. For a description of the circuit structure see the previous two applets.

In this demonstration, the output enable of the output cell blocks is set to low, enabling the tristate driver. Also, the XOR bit of each output cell is selected, so that the direct (non-inverted) output of the OR-gates is passed through to the Y_out output. Additional external inputs C and D have been added (on the right of the schematics), feeding back into the AND fuse matrix.

The programming in the upper GAL block implements the logical function (AB + AC + BC), resulting of the ORing together of the three terms (AB), (AC), and (BC) from the first, second, and third rows of the fuse matrix. (Keeping both the A and /A fuses intact in the fourth row results in a constant zero value for that row).

The programming of the lower GAL block implments the XOR function of inputs A and B.

     + = fuse ok
     . = fuse blown


     A /A  B /B  C /C  D /D     function 

     +  .  +  .  .  .  .  .     A AND B
     +  .  .  .  +  .  .  .     A AND C
     .  .  +  .  +  .  .  .     B AND C
     +  +  .  .  .  .  .  .     zero 
                                total:
                                        AB or AC or AD

     +  .  .  +  .  .  .  .     A AND /B
     .  +  +  .  .  .  .  .     /A AND B
     .  .  .  .  .  .  +  +     0
     .  .  .  .  .  .  +  +     0
                                total:   A xor B