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GAL output cell

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Circuit Description

This circuit shows the typical output cell block used for PAL and GAL programmable devices. It consists of three main components:

  • an n-input OR-gate followed by an XOR-gate,
  • a D-type flipflop,
  • a few multiplexers to select the routing of the input signals to the external output (on the right) and the feedback output (on the left).
By setting the input values to the control inputs, four different logical functions can be selected. When the SYN input is HIGH (1), the output value Y_OUT is the combinatorical OR of the A0..A3 inputs, while the XOR and AC0 inputs allow to select the polarity. At the same time, the feedback output X_out is directly connected to the Y_in pin.

On the other hand, when the SYN input is LOW (0), the output value Y_out is driven by the D-flipflop, while the polarity can again be selected by the AC0 and XOR inputs. Only the NQ (inverted) output of the flipflop is routed to the X_OUT feedback output.

The flexibility of this structure together with the programmable inputs allows the user to efficiently realize both combinatorical logical functions and finite state machines. The next applets will demonstrate a few examples.

Print version | Run this demo in the Hades editor (via Java WebStart)
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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/42-programmable/20-gal/GAL-ocell.html