Hades logoHades applet banner
ACTEL ACT1 mux-based XOR2 gate

applet icon

The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.)

Circuit Description

The ACT1 basic logic cell configured to implement a two-input XOR gate.

The A is connected to the second-level multiplexer and controls which first-level multiplexer drives the output Q. The B is connected to the control inputs of both first-level multiplexers, whose inputs are tied to low and high level to implement the XOR function of A and B.

If a third input signal C were available in both its non-inverted and its inverted form /C, this signal could be connected to the first-level multiplexer data-inputs in the obvious manner to construct a three-input XOR (parity/adder) gate.

Click the input switches or type the 'a' and 'b' bindkeys to control the applet.

Print version | Run this demo in the Hades editor (via Java WebStart)
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German)
Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/42-programmable/40-mux-fpga/ACT1-xor2.html