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GAL demonstration: basic logic functions

GAL demonstration:  basic logic functions screenshot

Description

This circuit shows the realization of basic logical functions using the PAL or programmable array logic structure. When used in combination with the output cell blocks, which can be used as either registered or simple combinatorical functions (when bypassing the flipflops), this structure is also often called GAL or generic array logic.

The example GAL structure shown here is kept almost to the bare minimum. It consists of two blocks, each of which has 32 fuses in the AND-matrix and one GAL output cell. The GAL has two external inputs A and B (on the left), whose direct and inverted values are fed into the first four columns of the AND-matrix. The direct and inverted output value of the upper GAL output cell block is fed back into columns 5 and 6 of the AND-matrix. Similarly, the direct and inverted output value of the lower GAL output cell block is fed back into columns 7 and 8 of the AND-matrix. Three additional fuses on top of each output cell block allow to select the behavior (combinatorical, registered, etc.) of the output cell block.

Naturally, real GAL devices typically have both more inputs and outputs (and correspondingly many more fuses) than the example circuit shown in the applet. The basic principle, however, is exactly the same. For example, a PAL16V8 has 8 dedicated inputs and 8 output cells. Each output cell is connected to and AND-OR matrix of size 32 columns by 8 rows. Seven of the rows are connected to the OR gate inside the output block, while the remaining row is routed separately. The number of 32 columns results from the true and complemented values of the 8 dedicated inputs and the 8 feedback inputs from the output cell blocks. Therefore, the AND-OR matrix of the whole PAL device has a total number of 32x64 fuses.

To keep the GAL schmematics simple and readable, a simplified symbol is used for the actual fuse-transistor connection between the column and row wires in the AND-matrix, where the solid diagonal line inside the gray rectangle indicates an intact fuse, while the blown fuse is indicated by the gray rectangle. The following image shows the conceptual circuit of one fuse connection, with the fuse connected to a diode. (Note that the actual realization in MOS-technologies would use a NOR-NOR matrix based on NMOS-transistors instead of the AND-OR matrix based on diodes.)

GAL Fuse structure and simplified symbol

From the AMD PAL Device Data Book (1980): Product terms with all fuses opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state: Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Unused input pins should be tied to Vcc or GND.

Put together, the GAL programming shown in the applet implements the following logical functions for each row of the GAL matrix:

     + = fuse ok
     . = fuse blown


     A /A  B /B  X /X  Y /Y     function 

     +  +  +  +  +  +  +  +     0        (all fuses ok)
     .  .  .  .  .  .  .  .     1        (all fuses open)
     +  .  .  .  .  .  .  .     A
     .  +  .  .  .  .  .  .     not A

     .  .  .  .  .  .  .  .     1
     .  .  .  .  .  .  .  .     1
     +  .  +  .  .  .  .  .     A AND B
     .  +  .  +  .  .  .  .     !(A AND B)

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Impressum | 24.11.06
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/42-programmable/20-gal/GAL-demo1_print.html