Each input of the cell can be connected to I/O pins or outputs from the same or other cells via the interconnection network. Click the input switches or type the '1' .. '8' bindkeys to control the eight inputs to the logic cell.
See the next few applets for example logic functions realized with this multiplexer based cell. The design software for these FPGAs uses special logic-synthesis algorithms which can efficiently map arbitrary circuits onto the multiplexer based cells.
Warning: the multiplexers used in the ACTEL datasheets (and most books showing the ACTEL architecture) use the opposite data-input ordering (A0/A1) as the Hades 2:1 multiplexer (hades.models.gates.Mux21). This makes no functional difference, but means that the layout of the circuits shown in the following applets are permutations of the circuits shown in the databooks.
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