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Hades
Applets
contents
visual index
introduction
std_logic_1164
gatelevel circuits
delay models
gate vs. wir...
gate delay d...
ring oscillator
hazards
NAND-chain
D-flipflop h...
clock-doubler
2-phase cloc...
flipflops
adders and arithm...
counters
LFSR and selftest
memories
programmable logic
state-machine editor
misc. demos
I/O and displays
DCF-77 clock
relays (switch-le...
CMOS circuits (sw...
RTLIB logic
RTLIB registers
Prima processor
D*CORE
MicroJava
Pic16 cosimulation
Mips R3000 cosimu...
Intel MCS4 (i4004)
image processing ...
[Sch04] Codeumsetzer
[Sch04] Addierer
[Sch04] Flipflops
[Sch04] Schaltwerke
[Sch04] RALU, Min...
[Fer05] State-Mac...
[Fer05] PIC16F84/...
[Fer05] Miscellan...
[Fer05] Femtojava
FreeTTS
The applets in this chapter demonstrate a few important aspects of circuit timing, including the fundamental wire-delay and gate-delay models, and examples of hazards.
Gate vs. wire delay demonstration
applet
webstart
print
Gate delay demonstration
applet
webstart
print
Ring oscillator
applet
webstart
print
Hazards and delay padding
applet
webstart
print
NAND-chain hazards demo
applet
webstart
print
D-flipflop hazards demo
applet
webstart
print
Clock-doubler with delay line
applet
webstart
print
Two-phase non-overlapping clock generator
applet
webstart
print
Usage
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Tutorial (PDF)
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Referenzkarte (PDF, in German)
Impressum
http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/10-delaydemo/gate-vs-wire-delay.html