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Circuit Description

As demonstrated by this applet, even simple circuits which implement the same logical function can have very different total delays.

The first and most obvious reason is a different circuit topology, as indicated by the second and third circuits on the page. The tree structure used in the third circuit means that the longest path from one input to the output goes through two gates, resulting in a total delay of twice the AND-gate delay. On the other hand, the serial connection of the gates in the second circuit means that the longest path (from A1/B1 to Y1) goes through three gates, implying a total delay of three AND-gate delays. However, the path from D1 to Y1 has a delay of only one AND-gate delay, which is faster than in the tree-structured circuit.

The second reason is due to technology constraints. For example, an AND gate in CMOS technology is actually constructed as the series connection of an inverting NAND gate and a standard inverter. Similarly, an OR gate is actually constructed from a NOR gate and an inverter. This implies that the gate-delays of AND and OR gates are the sum of the delays of the basic NAND/NOR gate and the inverter, resulting in a delay ratio of roughly 3:2:1 for the two-input gates, AND2:NAND2:INV and OR2:NOR2:INV. Not surprisingly, de-Morgan's rules are usually applied during logic minimization in order to avoid the slower AND/OR gates whenever possible.

Almost all current microprocessors and digital systems use a central clock signal to control all subsystems. In such circuits, the highest possible clock frequency is limited by the slowest path from one clocked element (=flipflop) to the next clocked element. The maximum clock frequency is then the reciprocal of the delay through that path of the logic plus the setup and hold time of the flipflops. Therefore, much effort during logic optimization is spent to design circuits, where almost all critical paths are balanced, until many paths in the overall circuit have almost the same delay. In microprocessors the slowest component is often the floating-point ALU (Note that the memory access is usually so slow that it has to be done in several dozen or hundreds of cycles, and therefore does not limit the clock frequency).