| Clock-doubler with delay line
Circuit Description
The clock-doubler circuit presented in this demonstration uses a trick
to create an output signal with two pulses for each input pulse.
However, the output signal is not symmetrical, and the circuit
operation relies on the exact propagation delay through the
delay-line feedback path (which is unpredictable due to tolerances).
In short, while the circuit is fun and a good illustration of gate delays,
it should never be used in real designs.
The main feature is the XOR gate in the clock line of the flipflop.
While the flipflop itself is triggered by the rising edge of its
clock input, the XOR gate allows inverting the input clock signal
- and therefore to toggle whether the flipflop reacts to the
rising or falling edge of the clock signal.
Every time the flipflop output changes, the feedback path changes
the upper input value of the XOR gate, which in turn toggles its output value.
As a result, the flipflop will be clocked at both edges (rising and falling)
of the input clock signal.
To watch the circuit, you may want to play with the input clock
frequency and duty-cycle,
and the gate delay properties of the gates in the feedback path.
Try to add probes (menu or popup-menu -> wire -> add probes)
on the input line, output line, and the feedback line.
The following images shows an example of the waveforms with
the default timing parameters, namely a symmetric input clock signal
of 0.25 Hz and a total delay through the inverters of 0.6 seconds.
Note that the duration of the 1-phase of the output clock signal
is the same as the delay through the delay inverters.
In a real circuit, the gate delay through the delay path will be
only a few nanoseconds, and therefore the duration of the
output clock pulses will also be only a few nanoseconds.
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introduction
delay models