The applets in this chapter demonstrate the simulation of the Femtojava processor studied by Prof. Ricardo Ferreira and his group from the Universidade Federal de Vicosa (Brazil). The Sashimi FPGA-design tools from the Universidade Federal do Rio Grando do Sul were used to develop the processor and its workloads.

Femtojava provides a testbed for evaluating microcontrollers on typical embedded systems workloads, with an emphasis on dynamic power-estimation and low-power design. Programs for Femtojava are written in a subset of Java, compiled to bytecode, and then executed on the processor. For details about the software development process with references to papers, presentations, and tutorials, see the applet pages below.

Several different implementations of the Femtojava architecture have been studied, ranging from a straightforward microprogrammed multi-cycle implementation to a pipelined processor with custom hardware accelerators.

Further reading:

• First step during selection sort
• Reconfigurable Java architecture

The following applets demonstrate three variants of Femtojava:

• the abstract behavioral model.
• the basic multi-cycle microprogrammed implementation.
• the pipelined implementation (synthesized via Sashimi).

	Femtojava processor: adder	applet	webstart	print
	Femtojava processor: factorial	applet	webstart	print
	Femtojava processor: interactive calculator	applet	webstart	print
	Femtojava processor structure (multicycle)	applet	webstart	print
	Femtojava processor: bubblesort demo	applet	webstart	print
	Femtojava processor: insertion-sort	applet	webstart	print
	Femtojava processor: quicksort demo	applet	webstart	print
	Femtojava processor structure with pipeline.	applet	webstart	print
	Quicksort demo on the pipelined Femtojava processor	applet	webstart	print