| |
DescriptionThis NOR-flipflop based circuit implements
a non-overlapping two-phase clock signal generator
and can be used to derive a two-phase clock signal from a
single and possibly non-symmetrical clock signal.
For an explanation of the circuit and a
detailed discussion of circuit clock strategies see
N.H.E.Weste and K.Eshragian, Principles of CMOS design, 1993,
section 5.5.10.
While the upper circuit uses 'typical' gate-delays in the nanosecond range,
the bottom circuit uses slowed-down gate-delays of 0.2 seconds per gate.
This should make it easier to observe the idea behind the circuit.
A few example waveforms to illustrate the timing:
