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Circuit Description

A demonstration of the RTLIB dual-port random-access memory component (hades.models.rtlib.memory.DPRAM).

The component shown here has two fully separate read-ports (data outputs), each controlled by their own address input. Therefore, any two memory cells can be read in parallel.

However, the DPRAM has only one input port, controlled by the write-enable input and the address A address input. Naturally, it would also be possible to provide a third address input for the write address, but the variant shown here is typical for the so-called two-address machines. These are microprocessors whose arithmetic instructions read two registers and overwrite one of the registers with the result:

  reg_a = reg_a  .op.  reg_b