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Circuit Description

A demonstration of the RTLIB user-configurable address-decoder component (class hades.models.rtlib.memory.AddressDecoder4).

This simulation model provides an easy means to include a custom address-decoder (or similar user-configurable comparator) into a Hades RTLIB design. The component takes one n-bit input value and generates four low-active output signals suitable for the chip-select inputs of RTLIB memory components. (For high-active outputs, simply add inverters.)

The property-sheet (popup-menu, edit component) of the address-decoder lets you select the input bus width and four independent offset and limit values for each of the four outputs. Each output is active (low), when the input value is inside the interval defined by [offset,limit] (or start-address, end-address). For example, if offset=0x4c and limit=0x51, the corresponding output will be active for the input values 0x4c, 0x4d, 0x4e, 0x4f, 0x50, and 0x51.

In the example, the following values are preset:

   output offset limit     example meaning
   nCS0   0x0000 0x6fff    28 KBytes RAM
   nCS1   0x7000 0x7003    4 bytes I/O
   nCS2   0x7004 0x7005    2 bytes I/O
   nCS3   0x8000 0xffff    32 KBytes ROM