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Circuit Description

A demonstration of the RTLIB level-triggered latches (with and without reset input).

Just click the input switches to play with the standard latch register (set to 8 bit width) on the left part of the schematics. When the clk input is high, the latch is transparent and propagates its D input value to the Q output. As soon as clk goes low, the latch becomes passive and stores the current value.

The logic on the right part of the applet again illustrates the common master-slave design approach for latch-based circuits with feedback path. Two latches controlled by separate, non-overlapping clock signals are used to avoid races through transparent latches.

Note: for sake of simplicity, an overlapping two-phase clock signal is used in the applet (when clock goes low, nclock is still high due to the delay of the inverter. This only works here, because the propagation delays of the latches are longer than the inverter delay.) For real designs, a non-overlapping two-phase clock signal would be used.