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Circuit Description

A demonstration of the RTLIB ShiftRegR n-bit shift-register with asynchronous reset input (class hades.models.rtlib.register.ShiftRegR).

As long as the shift/nload switch connected to the shift-register ena input is tied low (0), the register behaves like the normal edge-triggered register with asynchronous reset (RegR). The SOUT output pin is internally connected to the output of the least-significant bit register (index 0).

If the shift/nload (ena) input is driven high (1), the register functions like a standard shift-register. On the each rising edge of the clock input signal, the current data value inside the register is shifted one bit right, and the current input value from the SIN input is loaded into the leftmost (most significant) register.

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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/50-rtlib/20-registers/shiftreg.html