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counters
asynchronous... asynchronous... frequency di... synchronous ... synchronous ... up/down counter asynchrounou... 749x counters 7493 1:16 co... 7490 1:10 co... 7492 1:12 co... 74590 counter 74390 decima... frequency co... pulse-generator digital clock digital clock LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTSThe counter consists of two separate stages of a single JK-flipflop (1:2) and three JK-flipflops (1:6, asynchronous). The reset inputs (R01 and R02) are shared by all flipflops.
For the full 1:12 counter, the output of the first stage QA is connected to the clock input nB of the 1:6 counter stage. Note the counting sequence 0,1,2,4,5,6 of the 1:6 counter. This was probably preferred over the 0,1,2,3,4,5 sequence due to its cheaper implementation (note that no additional gates are required in front of the JK-flipflops).