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Circuit Description

This applet shows the realization of asynchronous counters with JK-flipflops, where the output of one flipflop is used as the clock input to the next flipflop, while both the J and K inputs of each flipflop are connected to a logical 1.

Click the input switches or type the 'c' and 'd' bindkeys to watch the circuits.

Both J and K being one, each flipflop toggles its state on the active (here, falling) edge of its clock signal. Therefore, the Z0 output of the first flipflop toggles at every second active edge of the input clock signal. As this output signal is the clock input to the second flipflop, the Z1 output of the second flipflop toggles at every fourth edge of the input clock, etc.

Depending on whether the clock input of one stage is connected to the Q or NQ output of the preceding stage, it is possible to count up or down.

Finally, note that the flipflops do not toggle at the same time. Rather, the reaction of each flipflop is delayed with respect o the previous stage - the counter operates asynchronously.