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Circuit Description

The asynchronous counter (JK flipflops) applet again, but slowed down to make the behaviour explicit. The JK-flipflops are again used as toggle-flipflops with both their J and K inputs connected to a logical 1, so that the flipflop toggles its current value on the (falling) edge of the input clock.

Click the input switches or type the 'c' and 'd' bindkeys to watch the circuits.

In order to show that the flipflops do not toggle at the same time, a very large flipflop input-to-output propagation-delay of 0.1 seconds is used in the applet. Therefore, it is easy to observe how a new counter value ripples through the counter.

Both J and K being one, each flipflop toggles its state on the active (here, falling) edge of its clock signal. Therefore, the Z0 output of the first flipflop toggles at every second active edge of the input clock signal. As this output signal is the clock input to the second flipflop, the Z1 output of the second flipflop toggles at every fourth edge of the input clock, etc.

Again, depending on whether the clock input of one stage is connected to the Q or NQ output of the preceding stage, it is possible to count up or down.