|TAMS / Java / Hades / applets: contents | previous | next|
adders and arithm...
7493 1:16 co...
7490 1:10 co...
7492 1:12 co...
LFSR and selftest
I/O and displays
CMOS circuits (sw...
Mips R3000 cosimu...
Intel MCS4 (i4004)
image processing ...
[Sch04] RALU, Min...
|TTL-series 74590 8-bit counter with tri-state outputs
This applet shows the TTL-series 74590 integrated circuit,
an 8-bit counter with latched tri-state outputs.
This circuit can be decomposed into three major components: first, an eight-bit counter (with enable via the nCCKEN input), second, an eight-bit register triggered by the RCK clock input, and third an eight-bit tri-state driver controlled by the nG input.
Both the counter and the output register are sensitive to the rising edges of their respective clock inputs (CCK and RCK). If both clocks are driven by the same signal, the output-register value will be one-less than the current counter value, because both register transition at the same time. The tri-state drivers are enabled when nG is low and tri-stated when nG is high. The nRCO output can be connected to the nCCKEN input of another 74590 counter to cascade multiple counters.
Click the input switches, or type the 'c' (counter clock), 'd' (register clock), 'e' (counter enable), 'g' (output enable) and 'r' (reset) bindkeys to control the circuit.
Note: The actual 74590 circuit uses a synchronous 8-bit counter with multiple-input AND gates for its carry tree. The applet, however, is based on an asynchronous counter. The diagonal wiring makes the structure of the carry-chain explicit, and also saves some valuable screen space. Finally, metastable JK-flipflops have been used, because the SN74590 counter component had to be used in a legacy-schematics without explicit reset inputs. Therefore, the circuit will be initialized to a random state at the start of the simulation.
|Print version | Run this demo in the Hades editor (via Java WebStart)|
|Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German)|