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Circuit Description

A demonstration of a typical two-address microprocessor datapath, built from a three-port register-file and a multifunction arithmetic-logic unit.

The instruction set of several 16-bit microprocessors includes arithmetic and logic instructions that operate on two different registers (so-called 2-address instructions). Two registers provide the source operands for the operation, and the first of the registers is also used to store the operation result. For example,

  reg_0  = reg_0   "+"   reg_1
  reg_12 = reg_12 "AND"  reg_3
  reg_1  = reg_1  "XOR"  reg_1
  ...

Typically, about 16 registers are provided, so that 4 bits are sufficient to address one register, and 8 bits are required to specify 8 registers. This easily fits into a 16 bit instruction word. (On the other hand, three register addresses would require 12 bits, which would leave only 4 bits for an instruction opcode.))

Obviously, a memory component with two independent read-ports and one write-port is required to support 2-address operations. The applet again includes the corresponding RTLIB RegBank component (class hades.models.rtlib.memory.RegBank), but the same address is used for the write-port and one of the read-ports. Unlike the standard asynchronous RAM component, write-operations are controlled by the clock signal. Open the memory editor (popup-menu, edit component) to edit the register file contents and to watch the read- and write-accesses.

To execute an arithmetic or logic operation, first select the ALU function and the two memory addresses via the corresponding IpinVector switches. Then enable the ALU output tri-state buffer, select write-enable (active low), and generate a clock pulse (rising edge) to write the ALU output data to the selected target register.

Unlike the previous applet (three-address datapath), this applet also includes an extra flipflop to store the carry-output value from the ALU. As the flipflop feeds the carry-in input of the ALU, multiple-word arithmetic operations (like 32-bit or 64-bit additions) are possible.