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Circuit Description

A demonstration of the generic RTLIB random-access memory component with separate active-low chip-select, write-enable, and output-enable control signals (class hades.models.memory.RAMoe). As usual for on-chip components, separate data-input and data-output ports are provided.

The RAMoe memory uses tri-state outputs controlled by the (active-low) output-enabled control signal, so that the memory output can be connected directly to the data-bus driven by multiple components. The RTLIB also includes a basic RAM component for random-access memories without tri-state output. Data is written to the RAM while the chip-select (nCS) and write-enable (nWE) inputs are both active (low).

Open the memory editor (popup-menu, edit component) of the RAM to watch the memory access and to edit the memory contents. The memory cell last read is highlighted in green color, while the memory cell last written is highlighted in magenta color.

Use the several menu commands of the memory editor to specify the memory size (number of words, bits per word), to load and save memory data from and to files, etc. Note that the memory editor will not fully update its user-interface when you change the memory size (this is a known but minor bug). Please close and re-open the design file to re-initialize the memory editor with the new memory size.