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Circuit Description

A demonstration of the D*CORE RAM (random-access memory) RTLIB component. This applet is used in the context of the T3 laboratory course to introduce the behaviour of standard SRAM integrated circuits.

The electrical interface of the D*CORE RAM component is the same as the generic RTLIB random-access memory (see the RAM demonstration applet), with separate data input port, tri-state data output port, and asynchronous low-active chip-select, output-enable, and write-enable signals. The memory size is set to 1024 words of 16 bit each.

Note that the memory editor (popup-menu, edit component) includes the option to disassemble the memory-contents, using the D*CORE instruction-set. From the memory editor menu, select edit-format-hex for the standard hexadecimal memory dump, or edit-format-disassemble to switch to the disassembled memory view. (The instruction set is loosely based on the Motorola M*CORE instruction set, with the typical two-operand format used by 16-bit RISC processors.)

For details, check the course material (in German) on our webserver.