incrementer and decrementer


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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic input and ou... configuration animation incrementer adder subtraction rotate shifters comparison logic (bitwise) logic (wordw... muxes bit-twiddling bus-tap expand bits tri-state bu... RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		incrementer and decrementer The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description A demonstration of four RTLIB arithmetic operators: incrementer, incrementer-by-two, decrementer, and two's-complement. All components are set to 8-bit bus-width. Click the input switch (again, shift-click to decrement, control-click for U and Z) or type the 'a' bindkey to control the circuit.

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Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/50-rtlib/10-components/incr.html