bus-tap components


		TAMS / Java / Hades / applets: contents \| previous \| next


Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic input and ou... configuration animation incrementer adder subtraction rotate shifters comparison logic (bitwise) logic (wordw... muxes bit-twiddling bus-tap expand bits tri-state bu... RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		bus-tap components The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description The bus-tap components (classes hades.models.rtlib.io.BusTapRight and BusTapBottom) provide the same function as the subset (hades.models.rtlib.io.SubSet) component: they extract a subset of the bits of their multiple-bit input signal. Unlike subset, the bus-tap components are inconspicuous in your schematics.

		Print version \| Run this demo in the Hades editor (via Java WebStart)

		Usage \| FAQ \| About \| License \| Feedback \| Tutorial (PDF) \| Referenzkarte (PDF, in German)

Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/50-rtlib/10-components/bustap.html