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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock DCF-77 clock shifter loadable cou... loadable cou... wait-intervals wait-counter decoder FSM relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS | Shift-register (59 bit)
Circuit Description
A 59-bit shift register.
This register is clocked once a second,
with the data input driven by the current output of the decoder
state-machine.
Each bit clocked into the shift register corresponds to one
bit of the DCF-77 time signal.
At the end of a one-minute transmission,
the shift register hold the complete DCF-77 time data for the
following minute, in the order specified by the DCF-77 time code.
The flipflops that holds the hours, minutes, and seconds data are connected to output ports. The values on these ports are read and loaded into the output registers of the DCF-clock as soon as the decoder state-machine detects the start of a new minute.
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Print version | Run this demo in the Hades editor (via Java WebStart) | ||||
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German) | ||||
Impressum | http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/45-misc/80-dcf77/Shifter59.html |