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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos LED sign RS232 transm... RS232 transm... controller shift-register input-buffer RS232 receiv... RS232 receiver controller shift-register output-buffer FSK modem FSK modulator I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS | serial-in parallel-out shift-register
Circuit Description
A simple serial-in parallel-out shift-register.
Use mouse-clicks or type the bindkeys 'c' and 'd' to control the clock and data inputs. All flipflops are connected to the same clock signal. We need no extra reset signal here, because new data is continually shifted into the register and the controller block guarantees that the output of this register is read-out in the correct moment. The assignment of the output ports reflects the bit-order used by the RS-232 protocol, with the least-significant bit of the data transmitted first, followed by the next data bits, and finally the parity bit (if any).
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Print version | Run this demo in the Hades editor (via Java WebStart) | ||||
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German) | ||||
Impressum | http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/45-misc/31-receiver/shifter.html |