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Circuit Description

Another simple demonstration of the JavaFSM state machine editor. The applet shows one possible realization of an transmitter for the RS232 serial protocol (8N1) using a parallel data register and an multiplexer. (An alternative implementation is to use a shift-register instead of the parallel register and multiplexer.)

First, select the data word to be transmitted using the switches D7 .. D0. Next, set the send switch to its on-state and wait for the next rising clock edge to latch the data input into the data buffer registers, and to start the transmission sequence. The state machine enters its start state, followed by a transition through the states d0,d1,d2,d3,d4,d5,d6,d7, and then either the stop or wait states on the next clock cycles. The state machine outputs control the multiplexer to output the corresponding states required by the RS232 protocol, namely the start bit (0), the eight data bits (D0 .. D7), and one stop bit (1).

Depending on whether or not the send switch was toggled back to the off-state, the machine will wait in either its wait or idle states. For the next transmission, select the send-switch again and wait for the next rising edge of the clock.

What changes are required to implement the 8O1 protocol with one start bit, eight data bits, one even-parity bit calculated from the eight data bits, and 2 stop bits?