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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor counter counter with... counter up-down counter up-d... man-wolf-goa... branch-predi... stack contro... traffic ligh... RS232 transm... misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS | up-down counter
Circuit Description
Another counter realized with the interactive state-machine editor,
namely an up/down counter.
Please check the basic counter applet for an overview of the state-machine-editor and for the description of the basic seven state counter with binary encoded outputs. Click the input switches or type the 'c' and 'u' bindkeys to generate the clock pulses and to control the up/down input. In the applet shown here, the 'UP/nDOWN' input and several transitions have been added to the counter state machine. Depending on the value of the 'UP/nDOWN' during a rising edge of the clock, the counter counts up (0,1,2,3,4,5,6,0) or down (0,6,5,4,3,2,1,0). Again, note that the state machine indicates the currently active transition in its symbol.
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Print version | Run this demo in the Hades editor (via Java WebStart) | ||||
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German) | ||||
Impressum | http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/45-misc/05-fsm-editor/counter-updown.html |