The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.)

Circuit Description

This circuit shows the typical output cell block used for PAL and GAL programmable devices. It consists of three main components:

• an n-input OR-gate followed by an XOR-gate,
• a D-type flipflop,
• a few multiplexers to select the routing of the input signals to the external output (on the right) and the feedback output (on the left).

On the other hand, when the SYN input is LOW (0), the output value Y_out is driven by the D-flipflop, while the polarity can again be selected by the AC0 and XOR inputs. Only the NQ (inverted) output of the flipflop is routed to the X_OUT feedback output.

The flexibility of this structure together with the programmable inputs allows the user to efficiently realize both combinatorical logical functions and finite state machines. The next applets will demonstrate a few examples.