Applets
contents
visual index
introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest
memories
ROM circuit 1Kx8 ROM demo RAM structure RAM write-cycle RAM read-cycle RAM write-ha... RAM storage ... RAM address ... RAM bitline ... 74189 SRAM 74219 SRAM 74219 SRAM a... 6116 CMOS SRAM multiple SRAMs programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTSThe nWE (active-low write enable) signal controls the tri-state buffer that drives the bitline. While nWE is high, the tri-state buffer is disabled and the bitline is not driven. When nWE is low, the data input is driven onto the bitline.