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Circuit Description

This circuit demonstrates how to use two ClockGen components to generate a two-phase non-overlapping clock signal. The basic idea is to use the same period for both clock generators, but to use different offset timing parameters in order to delay one generator with respect to the other.

The timing parameters chosen in the demo use a delay of one-half period and a small duty-cycle to generate a non-overlapping two-phase clock. The large period (2 seconds) used in the demonstration allows to watch the clock signals easily, but the same concept can also be applied to more realistic clock frequencies like a few megahertz.

In circuits with flipflop components, you might want to include a PowerOnReset component with corresponding timing parameters. The reset pulse should last until both clock generators are running, and it should not end near the active edge of either of the clocks.