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D*CORE program counter logic

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Circuit Description

A demonstration of the D*CORE processor program counter logic. This applet is used in the context of the T3 laboratory course for interactive exploration of a typical microprocessor control-unit.

The applet shows the logic used to generate both the normal sequential control flow and the several variants of jumps in the D*CORE processor. The PC register always stores the address of the current program instruction; the tri-state driver is enabled during the corresponding cycles of the instruction-fetch microcode to drive the internal data-bus and transfer the PC contents to the MAR register.

The 4:1-multiplexer is used to load one of four different values into the PC register:

  • the left-most path through the multiplexer allows loading the value zero into the PC register; this can be used during the processor initialization (power-up) sequence or interrupt sequences to provide a well-defined initial start address.
  • the second path through the multiplexer is driven by an IpinVector switch in the applet; this allows to directly load an instruction into the PC register. In the complete processor, the corresponding path is driven by the X output port of the register file; this is used for the PC := regX jump instruction.
  • the third path through the multiplexer is driven by the output of the adder; this is used for the PC-relative branch instructions.
  • during normal program execution, the rightmost path through the multiplexer allows loading the PC with its current value incremented (by 2), or PC := PC + 2. Given the instruction size of 16 bits and the byte-addressing, the increment of 2 corresponds to the next sequential instruction address.

For details, check the course material (in German) on our webserver.

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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/60-dcore/t3/next-pc.html