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D*CORE address decoder (memory map)

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Circuit Description

A demonstration of the address-decoder component used in our T3 laboratory D*CORE processor.

The address-decoder takes the current memory address as its input and generates three output signals:

  • nCS_ROM is used to enable the read-only memory component (active low), in the address range 32767..65536 (0x8000..0xffff). The ROM component is used to store the D*CORE programs.
  • nCS_RAM is used to enable the random-access memory component (active low) in the address range 0..28671 (0x0000..0x6fff).
  • CS_TERM is used to enable the parallel-terminal component at address 28672 (0x7000).

For details, check the course material (in German) on our webserver.

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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/60-dcore/t3/addr-decoder.html