D*CORE address decoder (memory map)


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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE counter bus and flip... RAM address decoder memory subsy... datapath microcode se... program counter processor processor an... Sieve of Era... MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		*DCORE address decoder (memory map) The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description A demonstration of the address-decoder** component used in our T3 laboratory DCORE processor. The address-decoder takes the current memory address as its input and generates three output signals: nCS_ROM is used to enable the read-only memory component (active low), in the address range 32767..65536 (0x8000..0xffff). The ROM component is used to store the DCORE programs. nCS_RAM is used to enable the random-access memory component (active low) in the address range 0..28671 (0x0000..0x6fff). CS_TERM is used to enable the parallel-terminal component at address 28672 (0x7000). For details, check the course material (in German) on our webserver.

		Print version \| Run this demo in the Hades editor (via Java WebStart)

		Usage \| FAQ \| About \| License \| Feedback \| Tutorial (PDF) \| Referenzkarte (PDF, in German)

Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/60-dcore/t3/addr-decoder.html


		TAMS / Java / Hades / applets: contents \| previous \| next


Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE counter bus and flip... RAM address decoder memory subsy... datapath microcode se... program counter processor processor an... Sieve of Era... MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		*DCORE address decoder (memory map) The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description A demonstration of the address-decoder** component used in our T3 laboratory DCORE processor. The address-decoder takes the current memory address as its input and generates three output signals: nCS_ROM is used to enable the read-only memory component (active low), in the address range 32767..65536 (0x8000..0xffff). The ROM component is used to store the DCORE programs. nCS_RAM is used to enable the random-access memory component (active low) in the address range 0..28671 (0x0000..0x6fff). CS_TERM is used to enable the parallel-terminal component at address 28672 (0x7000). For details, check the course material (in German) on our webserver.

		Print version \| Run this demo in the Hades editor (via Java WebStart)

		Usage \| FAQ \| About \| License \| Feedback \| Tutorial (PDF) \| Referenzkarte (PDF, in German)

Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/60-dcore/t3/addr-decoder.html