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Circuit Description

This applet demonstrates the RTLIB simulation components used to convert between single-bit (StdLogic1164) and multi-bit (StdLogicVector) representations.

The select-bit component (class hades.models.rtlib.io.SelectBit) extracts a single bit from its input bus.

The expander components (classes hades.models.rtlib.io.Expander and ExpanderVertical) take a SignalStdLogicVector as their input and split this into a set of individual SignalStdLogic1164 outputs. If only a few single bits are required from a wide bus, it might be a good idea to use an intermediate Subset or BusTap component to first select a subset of the wide bus before expanding it.

The clone-bits component takes a single input bit and replicates it to the selected bit-width.