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introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest
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ROM circuit 1Kx8 ROM demo RAM structure RAM write-cycle RAM read-cycle RAM write-ha... RAM storage ... RAM address ... RAM bitline ... 74189 SRAM 74219 SRAM 74219 SRAM a... 6116 CMOS SRAM multiple SRAMs programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTSWhen the applet is first loaded by your browser, the animation sequence starts automatically. It stops (pauses) the simulator once the animation is finished. Press the play button in the simulator control panel to continue with an interactive simulation (click the switches), or click the stop (rewind) and play buttons to re-start the animation sequence from the beginning.
The animation sequence also opens the waveform viewer. Depending on your operating system and window manager, you might have to move the waveform viewer window to the background in order to see the animation. After the animation has stopped, press the zoom fit button (or type the f bindkey) in the waveform viewer window to look at the timing of the write-cycles.
The write-cycle sequence starts after a few seconds. It first initializes the data-inputs to the value 0001b and the address input to 00b, and activates the nChipSelect input (active low). Next, the nWriteEnable input is activated (low) for one second. During this interval, the bit-line tri-state buffers drive the bitline with the current input value, which in turn overwrites the previous memory contents of the selected memory cell. Note that the memory contents are instantly propagated to the RAM data outputs via the output bitlines. Next, the nWriteEnable input is deactivated, which finished the first write operation.
The animation sequence then continues to write the data values 0010b, 0111b, and 1000b to addresses 01b, 10b, and 11b. Again, the data-inputs and address-inputs are initialized to the respective values, and nWriteEnable is then asserted for one cycle to write the selected memory cell.