Hades logoHades applet banner
TTL-series 74219 SRAM demonstration

applet icon

The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.)

Circuit Description

This applet demonstrates the TTl-series 74219 16x4 bit SRAM circuit. The memory matrix consists of 64 latches organized as 16 (2^4) words of 4 bits each, accessible via separate input and output lines. A 4 bit address input selects one of the 16 memory words.

Note: TTL family of integrated circuits also contains two other 16x4 bit RAM chips that are very similar to the 74219, namely, the 7489 and 74189 circuits. For some obscure implementation reason, both the 7489 and 74189 integrated circuits use inverted outputs - the values on the output bus are the inverse of the data previously written into the RAM. See the 74189 applet for a live demonstration.

Use the property editor (popup menu->edit) to open the user interface with the memory editor. It shows a table with the current memory data contents (hex encoded), with the memory addresses on the left and the data stored at the address on the right. Additionally, the memory word last read and written are highlighted in green and cyan colors (unless you use a personalized color scheme). To edit the RAM contents, move the mouse to the memory cell in question, click the left button, and then enter the new value as a hexadecimal number via the keyboard. The 74219 RAM only stores 4-bit per memory word, so that a single keystroke ('0' .. '9', 'a' .. 'f') is sufficient.

The behaviour of the 74219 circuit is controlled by just two active-low control lines, namely the nCE (chip enable) and nWE (write enable) inputs:

  • nCE=1: the data outputs are tri-stated and the clock signal for the latches in the memory matrix is disabled.
  • nCE=0, nWE=1: the data outputs are enabled and driven with the contents of the currently addressed memory word. When the address input is changed, the contents of the newly selected memory word will appear on the data outputs, delayed by the memory access time.
  • nCE=0, nWE=0: the clock signal of the currently addressed memory latches is enabled, so that the values on the data input bus is copied into the selected memory word (transparent latches). Also, the data outputs are enabled. Switch the nWE (write enable) signal back to the high (1) state to store the data.

To get accustomed to the behaviour of the SRAM, it is a good exercise to try to write a few data words into the memory (e.g. the values shown in the screenshot above).

Print version | Run this demo in the Hades editor (via Java WebStart)
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German)
Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/40-memories/40-ram/demo-74219.html