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LFSR and selftest
1Kx8 ROM demo
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RAM address ...
RAM bitline ...
74219 SRAM a...
6116 CMOS SRAM
I/O and displays
CMOS circuits (sw...
Mips R3000 cosimu...
Intel MCS4 (i4004)
image processing ...
[Sch04] RALU, Min...
|CMOS 6116 2Kx8 SRAM
This applet demonstrates the
CMOS 6116 SRAM circuit.
It consists of a memory matrix of 2048 (2K) words of 8-bit each,
addressed by 11 address inputs (A10 .. A0)
and accessed via 8 bidirectional data pins (D7 .. D0).
Due the the smaller transistor size and the much lower energy dissipation,
CMOS memories can be built with much higher capacity
than bipolar RAMs (like the 74189 demonstrated in the previous applet).
Naturally, current CMOS technologoy allows to manufacture much larger
memories than the 6116 with its 2 KBytes (which was popuplar on the
early 8-bit microcomputers).
Internally, CMOS SRAMs typically employ a standard six-transistor
storage cell that is somewhat smaller than a standard latch and also
allows for very efficient layout (by cell abutment).
Unfortunately, the six-transistor storage cell relies on certain
low-level electrical properties of the transistors that cannot
easily be modelled on the logical level. Therefore, a Hades
simulation model of the storage cell is not included in this applet
collection. Instead, please check out the dedicated
SRAM storage cell demonstration applet on our website.
Unlike the 74189-SRAM shown in the previous applet,
the 6116 integrated circuit uses a single data bus for both
read and write operations.
This is a typical organization for large external memories,
where the number of pins on the circuit package and the number
of signal wires on the boards determine the total system cost.
In fact, typical DRAM circuits with even higher memory capacity
often also use a multiplexed address bus in order to reduce
the number of pins required for the address inputs.
Again, selecting the property editor (popup menu->edit) on the 6116
simulation component opens the user interface with the memory editor.
Eight memory words are shown in each row of the memory.
The memory address corresponding to the first memory word of each row
is shown on the left, and the remaining words use the following seven
Additionally, the memory word last read and written are highlighted
in green and magenta colors (unless you use a personalized color scheme).
To edit the RAM contents, move the mouse to the memory cell in question,
click the left button, and then enter the new value as a hexadecimal
number via the keyboard.
The 6116 RAM stores 8-bit per memory word,
so that two keystrokes ('0' .. '9', 'a' .. 'f') are required to fill
one data word.
Each new keystrokes adds one hex-digit and shifts-out the previous
Type the space key or shift+space to navigate to the next or previous
The following screenshot shows the Hades editor running the 6116 RAM demo with the memory editor open:The behaviour of the 6116 circuit is controlled by three active-low control lines, namely the chip select, write enable, and output enable inputs:
|Print version | Run this demo in the Hades editor (via Java WebStart)|
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