Wait-Counter


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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock DCF-77 clock shifter loadable cou... loadable cou... wait-intervals wait-counter decoder FSM relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		Wait-Counter The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description A six bit synchronous counter connected to the 'WaitIntervals' subdesign. This counter is used by the 'DecoderFSM' state-machine to calculate the delay between the DCF-77 signal pulses. It is clocked with the 20 Hz clock signal, and reset whenever the decoder state-machine detects a new pulse. The three output signals generate by this subdesign correspond to 'one second' interval between pulses, 'two seconds' interval between pulses, and 'timeout' or 'missing signal'.

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Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/45-misc/80-dcf77/WaitCounter.html