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Circuit Description

This subdesign shows the 1-bit loadable synchronous counter block used to build the four-bit counters for the DCF-77 clock.

The nreset and clk inputs are directly connected to the D-type with reset flipflop (hades.models.flipflops.DFFR). The loadenable-input controls the 2:1 multiplexer in front of the D input of the flipflop. If loadenable is high, the value from the D input port is propagated to the flipflop and allows synchronous loading on the next rising clock edge.

Otherwise, the feedback logic is enabled. If nclear is low, the flipflop is reset on the next rising clock edge. If countEnable is high, the counter is enabled.