output-buffer register


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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos LED sign RS232 transm... RS232 transm... controller shift-register input-buffer RS232 receiv... RS232 receiver controller shift-register output-buffer FSK modem FSK modulator I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		output-buffer register The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description A standard 8-bit register built from D-type flipflops, used as the output-buffer of the RS-232 receiver. We don't need extra reset or enable logic here, because the receiver circuit design guarantees that the output-buffer (this register) is loaded before the strobe signal pulse is asserted to signal the arrival of a new character.

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Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/45-misc/31-receiver/reg8.html