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Hades
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A library of registertransferlevel componentsBesides the standard gatelevel simulation components like gates and flipflops, the Hades framework also provides an extensive library (called rtlib) of userconfigurable registertransferlevel simulation components. While the standard gates and flipflops are based on the std_logic_1164 multilevel logic system, the rtlib multiplebit simulation components are based on the std_logic_vector model and its arithmetic and logic functions. Naturally, one can easily mix standard and rtlib components (std_logic_1164 and std_logic_vector).Click the thumbnails below to see larger screenshots of three example circuits based on rtlib components. Check the applet collection for the interactive versions of the circuits. From left to right:
The rtlib library consists of the Java package hades.models.rtlib and its subpackages like hades.models.rtlib.arith or hades.models.rtlib.memory. Most of the multibit arithmetic and logic functions are provided by the class hades.models.StdLogicVector, while class hades.signals.SignalStdLogicVector is used for multibit signals. The current implementation is limited to buses at most 63bit wide, due to its use of a very compact storage scheme. Additional visualization aids are provided in the schematics editor to help understanding the behaviour of registertransfer level circuits:
Naturally, rtlib components can be used to construct more complex circuits. For example, click the following thumbnail to see a larger screenshot of our PRIMA processor ("primitive machine"), or click here to open the interactive applet version. The processor is kept as simple as possible, to teach the basics of the vonNeumann machine paradigm. The 8bit accumulator machine is built from just four registers (accumulator, program counter, instruction register, and address register), the ALU, one incrementer, two multiplexers, and the main memory:
 
Impressum  http://tams.informatik.unihamburg.de/applets/hades/webdemos/rtlib.html 