4-bit Register


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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops SR-Flipflop Flankensteue... JK-Flipflop Register [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		4-bit Register The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description Ein flankengesteuertes 4-bit Register mit den folgenden Funktionen: S1 S0 CLK E0..E3 \| Q0..Q3+ --------------------------------- * * 0 * \| Q0..Q3 (Wert gespeichert) * * 1 * \| Q0..Q3 (Wert gespeichert) 0 0 ! E0..E3 \| E0..E3 (Register laden) 0 1 ! E0..E3 \| In,Q0,Q1,Q0 (Shift-rechts) 1 0 ! * \| Q1,Q2,Q3,Q0 (Rotate-links) 1 1 ! * \| Q0..Q3 (Speichern)

		Print version \| Run this demo in the Hades editor (via Java WebStart)

		Usage \| FAQ \| About \| License \| Feedback \| Tutorial (PDF) \| Referenzkarte (PDF, in German)

Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/90-tionline/05-flipflop/4bit_register.html


		TAMS / Java / Hades / applets: contents \| previous \| next


Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops SR-Flipflop Flankensteue... JK-Flipflop Register [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		4-bit Register The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description Ein flankengesteuertes 4-bit Register mit den folgenden Funktionen: S1 S0 CLK E0..E3 \| Q0..Q3+ --------------------------------- * * 0 * \| Q0..Q3 (Wert gespeichert) * * 1 * \| Q0..Q3 (Wert gespeichert) 0 0 ! E0..E3 \| E0..E3 (Register laden) 0 1 ! E0..E3 \| In,Q0,Q1,Q0 (Shift-rechts) 1 0 ! * \| Q1,Q2,Q3,Q0 (Rotate-links) 1 1 ! * \| Q0..Q3 (Speichern)

		Print version \| Run this demo in the Hades editor (via Java WebStart)

		Usage \| FAQ \| About \| License \| Feedback \| Tutorial (PDF) \| Referenzkarte (PDF, in German)

Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/90-tionline/05-flipflop/4bit_register.html