PRIMA sequencer

Description

This applet shows the sequencer state-machine of the PRIMA processor.

The state machine has three states:

 flipflops   state       meaning                operation
 ---------- -------- -------------------------  ------------
     00      cycle1      fetch_instruction      BR = MEM[PC]; PC=PC+1
     01      cycle2      fetch_address          AR = MEM[PC]; PC=PC+1
     10      cycle3      execute_instruction    depends on BR

The AND gates are used to generate both a one-hot encoding of the states, useful for visualization (outputs 'cycle1_fetch' etc.) and three control signals which only depend on the sequencer state. These are the enable signals for the instruction register BR ('Befehlsregister'), address register AR, and the control signal for the adress selection multiplexer.

The remaining control signals depend on the contents of the instruction register BR, current accumulator contents, and overflow flag. See the control unit applet for the complete logic of the PRIMA control unit.

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