PRIMA processor (primitive machine)

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PRIMA processor (primitive machine)

Description

This applets shows a RT-level circuit realization of the PRIMA processor (primitive machine). This simple 8-bit accumulator machine is used as a first example of a von Neumann machine in our introductory lectures on computer science.

The 8-bit accumulator machine has the following main components:

random-access main-memory of 256 words (256x8)
8-bit accumulator, plus 1-bit carry/overflow register
8-bit ALU with 16 different operations
8-bit instruction register BR ('Befehlsregister' in German)
8-bit address register AR
8-bit program counter PC
hard-wired control logic STW ('Steuerwerk' in German)

The right side of the schematics shows the processor datapath with ALU, accumulator, and main memory. The next column of components to the left holds the program counter with assorted logic. During normal program execution, the program counter is incremented via the incrementer and the upper 2:1 multiplexer. For jump and branch instructions, this multiplexer is enabled, and the program counter is loaded with the current contents from the address register AR.

The lower multiplexer decides whether the RAM address is taken from the program counter (during the fetch_instruction and fetch_address cycles), or from the address register (for load and store instructions).

The BR register holds the current instruction; its output value is the main input to the control unit (on the lower left) that generates the several register-enable and multiplexer-control signals. In order to avoid cluttering the schematics with dozens of control signals, all control signals are drawn as a single bus that runs on the top of the schematics and connects to the several registers and muxes.

A few links to further documentation:

PRIMA instruction set
T1/T2 lecture page with detailed information and dozens of small example programs (in German).
PRIMA architecture simulator. This is another Java applet that demonstrates the behaviour of PRIMA on the architectural level without circuit details; includes a disassembler.

NOTE: To keep the schematics as readable as possible, the version of PRIMA demonstrated in this applet is slightly different from the original version shown in the lecture slides. First, the applet uses an 8-bit ALU and accumulator register instead of the full 9-bit variants required by the original specification. Also, the carry-out from the ALU and the ALU output are not used in the control-unit. This saves a lot of bit-twiddling and a few global buses that would run across the whole schematics.

The demo program used in this applet consists of just four instructions:

label  addr  data  mnemonic
             (hex)
       0     0f    LD1
       1     00
loop:  2     0a    INCR
       3     00
       4     48    ST 20
       5     20
       6     80    BR 2
       7     02

The program first loads the value 1 into the accumulator. It then increments the accumulator, store the result into memory address 20, and jumps back to the increment instruction. This is an endless loop, so that the program will continue to increment the accumulator value and save it to the memory over and over again.

Run the applet | Run the editor (via Webstart)

Impressum | 24.11.06
http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/50-rtlib/90-prima/prima_print.html