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DescriptionA 4-bit BCD-counter built with JK-flipflops.
This is an asynchronous implementation of a cascadable,
4-bit, binary-coded decimal counter.
In total, the circuits needs just the four flipflops and one
additional AND gate.
Click the clock switch or type the 'c' bindkey to operate the counter. (To keep the schematics as readable as possible, separate power-on-reset components are used for each flipflop in the example. No bindkeys are used for the power-on-reset components.)
The basic structure is just the asynchronous counter, with the Q output of one counter stage used as the CLK input for the next stage. Due to the AND-gate in front of its J input, the Z3 flipflop is only set when both Z1 and Z2 are 1 and Z0 generates a 0-1 edge. These conditions are only met when counting from seven to eight, correctly setting the Z3 flipflop. At the next clock input to Z3, while counting from nine to ten, the J input of Z3 is zero and the flipflop is reset to 0. At the same time, flipflop Z1 is also reset the NQ output of flipflop Z3 is still zero, inhibiting the transition of Z1 to 1, so that the counter correctly counts from nine to zero. The following image shows the timing diagram with the counter output, when the input clock frequency is very slow compared to the gate delays.
However, when zoomed into the timing diagram, the asynchronous nature
of the counter becomes clearly visible.
The individual flipflops do not toggle state at the same time,
but rather one after another.
While the asynchronous counter can be run at very high clock frequencies,
it is unsuitable for integration into synchronous designs.
For a detailed discussion of counters,
see (Jutzi, Digitalschaltungen, 4.3.3, p.137).
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