TAMS / Java / Hades / applets (print version): contents | previous | nextCMOS D-type transmission-gate flipflop
Description
A switch-level demonstration of the CMOS transmission-gate
rising-edge triggered D-type fliplop,
shown as a simplified gate-level schematics.
See the previous applet for the transistor-level schematics of
this circuit and the detailed explanation.
Click the input switches or type the 'c' and 'd' bindkeys to control
the clock and data inputs.
Run the applet | Run the editor (via Webstart)
Impressum | 11.01.07
http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/dff2_print.html